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标题: 烧录器PULL UP PULL DOWN疑问 [打印本页]

作者: program 时间: 2017-4-27 18:03
标题: 烧录器PULL UP PULL DOWN疑问
如题,当需要对IC脚位做pull up or pull down时,目前通用做法是要么全部IO up or DOWN, 没有单独控制哪个脚的功能.
这部分谁有新奇的想法.

作者: shangdawei 时间: 2017-5-2 00:22
来一串595单独控制可行否？

作者: program 时间: 2017-5-2 15:24
当然可以,但不解为什么没有单独控制.

作者: liyf 时间: 2017-5-2 18:46
全部上拉或下拉式有用途的，你要单独对某个脚上拉或下拉有什么用呢

作者: 古道热肠 时间: 2017-5-2 20:09
上拉一般是上拉到芯片的供电电压吧，这样保证FPGA输出的高电平与VDD保持一致。FPGA用的是OC门。

作者: shangdawei 时间: 2017-5-3 21:55
本帖最后由 shangdawei 于 2017-5-3 22:01 编辑

Drive 5V CMOS-Level Signals
A MAX V device can drive a 5.0-V TTL device by connecting the VCCIO pins of the MAX V device to 3.3 V.
This is possible because the output high voltage (VOH) of a 3.3-V interface meets the minimum high-level voltage of 2.4 V of a 5.0-V TTL device.

A MAX V device may not correctly interoperate with a 5.0-V CMOS device if the output of the MAX V device is connected directly to the input of the 5.0-V CMOS device.
If the MAX V device‘s VOUT is greater than VCCIO, the PMOS pull-up transistor still conducts if the pin is driving high, preventing an external pull-up resistor from pulling the signal to 5.0 V.

To make MAX V device outputs compatible with 5.0-V CMOS devices, configure the output pins as open-drain pins with the I/O clamp diode enabled and use an external pull-up resistor.

Must tri-state outputs and use an external resistor to pull up to 5V

To drive 5V CMOS-level inputs, a pull-up resistor must be applied to the 5V Virtex output.

Prior to driving a logic 1 data signal, the Virtex output must be tri-stated.

This ensures no overlap or crowbar current in the input buffers of the 5V-receiving device.

The required Virtex output pin configuration is commonly called “open collector”, or more correctly, “open drain”.

This function is easily generated inside the chip by driving the data together with the active low Output Enable signal of the output block.

The external low-to-high transition is then driven only by the pull-up resistor.

For example, applying a 470-ohm pull-up resistor to 5V and a 50-pF load capacitance (as shown in Figure 1) creates a 0.4V to 4.5V rise time of about 40 ns.

For a faster rise time, the internal active low Output Enable signal is not driven directly from the internal data signal.

Instead, it is driven from a two-input AND gate that is driven by both the internal data signal and the input signal returned from the same device’s output pin.

On the rising edge, this assures that the output pull-up transistor is active for most of the rise time, resulting in a shorter output delay.

The important part of the rise time from 0.4V to 3.0V is reduced dramatically, from 20 ns to 3 ns (see Figure 2).

Ringing can be avoided by following proper board design practices.

In most cases, the fast active edge enables the CMOS threshold to be passed with a propagation delay of less than 3 ns.

At worst, an additional pullup from the resistor is still needed to reach the threshold voltage reliably, but this enables at least 15 ns to be saved.

请教一下，最后的图片的原理是什么？

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