High Voltage to 3.3 V CMOS
Higher voltages (12 V to 18 V) typically come from outside the module. Any type of signals coming from
outside the module must have signal conditioning circuitry to limit noise spikes that can damage the
device from over current or over voltage.
Usually these circuits take the form of a voltage divider similar to the 5 V CMOS to 3.3 V CMOS case
above except that a capacitor must also be included from the device pin to ground to limit voltage
transients. Typically, test methods for automotive circuits require the inputs to survive 200 V spikes of
prescribed waveshapes.
The divider network R1/R2 is set to translate 18 V down to 3.3 V. 18 V is the maximum dc voltage that the
module expects to see from the charging system, even though 12 V is typical when the engine is off, and
cranking volts can be as low as 4 V. R1 must be set large enough to avoid exceeding the device pin’s
maximum input clamp current in the event that some rocket scientist uses double battery (24 V) to crank
the vehicle in the winter. The time constant of the parallel resistance (R1||R2) in combination with C1 is
set to absorb the 200 V spike without overstressing the input as well. It can quickly be observed that there
are more constraints than there are variables (if 4 V is a marginal "one" then 18 V will certainly forward
bias the input clamp circuit.) 作者: shangdawei 时间: 2014-11-25 23:57
高电压3.3 V CMOS
较高的电压（12V至18V）通常来自模块外。任何类型的信号，从未来
外的模块必须具有信号调节电路，以限制噪声尖峰，可以破坏
从设备过电流或过电压。
通常这些电路利用一个分压器类似于5伏CMOS至3.3 V的CMOS的情况下的形式
以上只是一个电容器也必须包括从设备引脚到地，以限制电压
瞬变。典型地，试验方法汽车电路所需要的输入生存200伏尖峰
规定的波形，。
