void InitPll（Uint16 val， Uint16 divsel）
{
// Make sure the PLL is not running in limp mode
if （SysCtrlRegs.PLLSTS.bit.MCLKSTS ！= 0）
{
// Missing external clock has been detected
// Replace this line with a call to an appropriate
// SystemShutdown（）; function.
asm（“ ESTOP0”）;
}
// DIVSEL MUST be 0 before PLLCR can be changed from
// 0x0000. It is set to 0 by an external reset XRSn
// This puts us in 1/4
if （SysCtrlRegs.PLLSTS.bit.DIVSEL ！= 0）
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
EDIS;
}
// Change the PLLCR
if （SysCtrlRegs.PLLCR.bit.DIV ！= val）
{
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = val;
EDIS;
// Optional： Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until
// the PLL is stable. Once the PLL is stable the CPU will
// switch to the new PLL value.
//
// This time-to-lock is monitored by a PLL lock counter.
//
// Code is not required to sit and wait for the PLL to lock.
// However， if the code does anything that is timing critical，
// and requires the correct clock be locked， then it is best to
// wait until this switching has completed.
// Wait for the PLL lock bit to be set.
// The watchdog should be disabled before this loop， or fed within
// the loop via ServiceDog（）。
// Uncomment to disable the watchdog
DisableDog（）;
while（SysCtrlRegs.PLLSTS.bit.PLLLOCKS ！= 1）
{
// Uncomment to service the watchdog
// ServiceDog（）;
}
EALLOW;
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
EDIS;
}
// If switching to 1/2
if（（divsel == 1）||（divsel == 2））
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
EDIS;
}
// If switching to 1/1
// * First go to 1/2 and let the power settle
// The time required will depend on the system， this is only an example
// * Then switch to 1/1
if（divsel == 3）
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
DELAY_US（50L）;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
EDIS;
}
}
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.XINT2 = &ISRExint; //告诉中断入口地址
EDIS; // This is needed to disable write to EALLOW protected registers
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block使能PIE
PieCtrlRegs.PIEIER1.bit.INTx5= 1; //使能第一组中的中断5
IER |= M_INT1; // Enable CPU 第一组中断
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
